//////////////////////////////////////////////////////////////////////////////////
/*!
    \file       sync_level_bus.v
    \author     Reid McClain
    \date       December 2019
    \version    
                20191205 \b Reid McClain    -   Initial code\n
    
    \copyright  Intel Restricted Secret -- Copyright 2019 Intel -- All rights reserved
*/

module sync_level_bus 
    #(
        parameter WIDTH  = 1
    )
    (
    // clock interface
    input wire             clk,
    
    // slave interface
    input wire [WIDTH-1:0] sync_in,     
    output reg [WIDTH-1:0] sync_out
    
);

reg [WIDTH-1:0] sync_meta;

    always @ (posedge clk) begin
      sync_meta <= sync_in;
      sync_out  <= sync_meta;
    end

endmodule
